1. Field of the Invention
The present invention relates in general to semiconductor integrated circuit (IC) design, and more specifically to the field of electronic design automation (EDA) for designing radiation-hardened CMOS integrated circuits.
2. Description of the Related Art
Radiation-hardened (“rad-hard”) integrated circuits are required for a wide range of commercial market applications, including medical and dental electronics (computed tomography x-ray scanners, implantables, etc.), avionics, space/satellite, and nuclear power systems, as well as military and defense systems. Currently-available rad-hard ICs, particularly those capable of surviving a high radiation dose of >300 krad (3000 Gy), depending on customer need, generally require the use of special materials, such as silicon-on-insulator (SOI) substrates, and a dedicated fabrication process. This results not only in extra expense in producing these devices, but more importantly, places the design and production of these devices outside the mainstream of leading-edge commercially-available ICs. The result is that rad-hard versions of high-performance commercial devices using commercial processes are not readily available for use in critical applications requiring high tolerance to radiation (like sterilization of implantable medical devices). In order for designers of rad-hard systems to obtain new rad-hard ICs, particularly those at advanced technology nodes, they are forced to accept longer time-to-market, compromises in performance, and significantly increased cost if they use the typical rad-hard IC development flow including a full custom design and its implementation in a specialty rad-hard process.
For example, there has been a typical 7-year performance gap (2+ generations) between space-qualified microprocessors and commercially-available processors. This corresponds to a dramatic potential performance improvement that could be achieved using state-of-the-art commercial processes as compared to >2 generations-behind rad-hard processes. The ability to use existing advanced standard processes would enable superior performance from the electronics, compared to special process flows and materials, and extend component life.
There is accordingly a need to enable the design and production of cost-effective rad-hard ICs using standard commercial CMOS and BiCMOS processes. Time to market would be much faster given the ability to convert existing commercial IC products to rad-hard versions, with changes only in the physical transistor design and layout.
CMOS hardness-by-design approaches use design techniques to overcome the inherent susceptibility of commercial CMOS technologies to radiation. [For example, see R. C. Lacoe et al., IEEE Trans. Nuclear Science, vol. 47, pp. 2334-2341 (2000).] A number of rad-hard device designs and layout techniques are known that can be used to improve the radiation performance of ICs, and a limited number of rad-hard libraries of standard cells for ASICs are available. But most rad-hard design continues to be a very manual process and follows the full custom design flow, depending greatly on the skill and knowledge of the designer. Thus there remains a need for EDA tools that can be used more generally to help convert existing commercial IC designs in order to improve their radiation-hardness performance, while maintaining their other cost and performance advantages.